Ulises Olivares
Departament of Electrical Engineering Center for Research and Advanced Studies of the National Polytechnic Institute, Mexico
Arturo García
Intel Corporation, USA
Félix F. Ramos
Departament of Electrical Engineering Center for Research and Advanced Studies of the National Polytechnic Institute, Mexico
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Published in: Proceedings of SIGRAD 2015, June 1st and 2nd, Stockholm, Sweden
Linköping Electronic Conference Proceedings 120:4, p. 13-16
Published: 2015-11-24
ISBN: 978-91-7685-855-4
ISSN: 1650-3686 (print), 1650-3740 (online)
This paper presents an efficient space partitioning approach for building high quality Bounding Volume Hierarchies using x86 CPU architectures. Using this approach a structure can be built faster than a binned-SAH heuristic while the structure preserves its quality. This method consists of a hybrid implementation that uses binned-SAH for the top level and a binary partitioning approach for the rest of the levels. As a result, this method produces more regular axis-aligned bounding boxes (AABB) into a complete quadtree. Additionally, this approach takes advantage of the 4-wide vector units and exploits the SIMD extensions available for current CPU architectures. Using our construction approach a structure can be built up to three times faster than binned-SAH.
