Conference article

Validation Method for Hardware-in-the-Loop Simulation Models

Tamás Kökényesi
Department of Automation and Applied Informatics, Budapest University of Technology and Economics, Hungary

István Varjasi
Department of Automation and Applied Informatics, Budapest University of Technology and Economics, Hungary

Download articlehttp://dx.doi.org/10.3384/ecp17142749

Published in: Proceedings of The 9th EUROSIM Congress on Modelling and Simulation, EUROSIM 2016, The 57th SIMS Conference on Simulation and Modelling SIMS 2016

Linköping Electronic Conference Proceedings 142:109, p. 749-754

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Published: 2018-12-19

ISBN: 978-91-7685-399-3

ISSN: 1650-3686 (print), 1650-3740 (online)

Abstract

The advances in FPGA technology have enabled fast real-time simulation of power converters, filters and loads. HIL (Hardware-in-the-Loop) simulators taking advantage of this technology have revolutionized control hardware and software development for power electronics. Switching frequencies in today’s power converters are getting higher and higher, so reducing calculation time steps in HIL simulators is critical, especially if simulating lower power circuits. Faster calculation can be achieved with simpler models or lower resolution. Both possibilities require the validation of the FPGA-synthesizable simulation models to check whether they are correct representations of the simulated main circuit or not. The subject of this paper is a validation method, which treats the simulation error similar as production variance, which can be measured between different instances of the original main circuit.

Keywords

circuit simulation, power circuit modeling, signal resolution, discrete-time systems

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