Conference article

Leadframe packages are always adopted as the low-end devices. When the low-cost channel including the leadframe package and the two-layer PCB is required for high-speed digital signaling over 1 Gb/s, the iteration of full channel simulation and analysis with reliable EDA tools should be taken before the device is rolled out. Different channel designs were characterized in the frequency domain using the 3-D full-wave electromagnetic field solver to analyze the bottleneck of channel performance. Comparison of the full channel S-parameters, the channel with the proposed DDR3 memory controller package suffers less insertion loss. The chip-package-board co-simulations in the time-domain using the chip HSPICE netlists and full channel S-parameters for the DDR3 data accessing at 1.2, 1.4, and 1.6 Gb/s were taken and demonstrated that the channel including the proposed package design had larger timing and voltage margins, and less jitter, overshoot and undershoot, which all conform to JEDEC Standard. The waveform measurement also verified the same prediction that the DDR3 memory controller encapsulated in the modified E-pad LQFP package achieved no cost impact and enough timing margin up to 1458 Mb/s. The performance of mature leadframe packages can be promoted if the careful package designs are taken.

DDR3, E-pad, LQFP, return path, S-parameters, jitter, eye diagram, JEDEC