Conference article

Translating Modelica to HDL: An Automated Design Flow for FPGA-based Real-Time Hardware-in-the-Loop Simulations

Christian Köllner
FZI Forschungszentrum Informatik, Karlsruhe, Germany

Torsten Blochwitz
ITI GmbH, Dresden, Germany

Thomas Hodrius
SET GmbH, Wangen/Allgäu, Germany

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Published in: Proceedings of the 9th International MODELICA Conference; September 3-5; 2012; Munich; Germany

Linköping Electronic Conference Proceedings 76:37, p. 355-364

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Published: 2012-11-19

ISBN: 978-91-7519-826-2

ISSN: 1650-3686 (print), 1650-3740 (online)


Advances in the development of electric vehicles challenge existing test methodologies and tools. In particular; hardware-in-the-loop test rigs to verify electric motor controllers require real-time drivetrain emulation with response times in the order of one microsecond. Field-programmable gate arrays can fulfill these requirements due to their high parallelism and the possibility to realize efficient and predictable I/O interfaces. We present an integrated methodology which translates Modelica models to VHDL hardware designs. Our methodology combines well-engineered algorithms from Modelica compilation and high-level synthesis for hardware. We demonstrate its capabilities using the example of a DC motor which was synthesized and implemented on a Xilinx Virtex-5 device.


Modelica; FPGA; High-level synthesis; VHDL; Hardware-in-the-Loop; Real-time


[1] Winkler D.; Gühmann C. Hardware-in-the-Loop simulation of a hybrid electric vehicle using Modelica/Dymola. Yokohama; Japan: The 22nd International Battery; Hybrid and Fuel Cell Electric Vehicle Sympo-sium & Exposition; Japan Automobile Research Institute; 2006

[2] Köhl; S.; Himmler; A.: Anwendungen und Trends bei der HIL-Simulation. Simulation und Test in der Funktions- und Softwareentwicklung für die Automobilelektronik II; expert verlag; Berlin; 2008; pp. 203-217

[3] SET GmbH Echtzeit-Emulation beschleunigt die Entwicklung; Funktions- und Leistungstests von E-Motor-Steuergeräten; Makt&Technik Vol. 27; 2010-05

[4] Liebau H.; Jakoby H.; Crepin; J.: HiL-Simulation elektrischer Fahrzeugantriebe. Automotive Engineering Partners; Vol. 2011-05

[5] Zhou Y. J.; Mei T. X.; FPGA based real time simulation of electrical machines; Proc. 16th IFAC World Congress; 2005

[6] Matar M.; Iravani R.; Massively parallel implementation of AC machine models for FPGA-based real-time simulation of electromagnetic transients; IEEE Trans-actions on Power Delivery; Vol. 26; No. 2; pp. 830-840 2011. doi: 10.1109/TPWRD.2010.2086499.

[7] Chen H.; Sun S.; Aliprantis D.; Zambreno J.; Dynamic simulation of electric machines on FPGA boards; Elec-tric Machines and Drives Conference; 2009

[8] Köllner C.; Yao H.; Müller-Glaser K. D.: Entwurfsme-thodiken zur Echtzeitsimulation physikalisch motivier-ter Modelle auf FPGAs: Eine Fallstudie. Methoden und Beschreibungssprachen zur Modellierung und Verifika-tion von Schaltungen und Systemen (MBMV); 2011.

[9] Dufour C.; Belanger J.; Lapointe V.; and Abourida S.; “Realtime simulation on FPGA of a permanent magnet synchronous machine drive using a finite-element based model;” Symposium on Power Electronics; Elec-trical Drives; Automation and Motion (SPEEDAM); 2008. doi: 10.1109/SPEEDHAM.2008.4581095.

[10] Nordström U.; López J. D.; Elmqvist H.; Automatic Fixed-point Code Generation for Modelica using Dymola; Proc. Intl. Modelica Conf.; 2006

[11] VHDL Analog and Mixed-Signal Extensions; IEEE Std. 1076.1-1999

[12] Coussy P.; Morawiec A. High-Level Synthesis: from Algorithm to Digital Circuit. Springer Netherlands; 2010.

[13] Grant M.; Smith G. High-Level Synthesis: Past; Present; and Future. Journal: IEEE Design and Test of Computers. Vol. 26; pp. 18-25; 2009. doi: 10.1109/MDT.2009.83.

[14] Nyström K.; Aronsson P.; Fritzson P.; Parallelization in Modelica; Proc. 4th Intl. Modelica Conf.; 2005

[15] Elmqvist H.; Otter M. and Cellier F.E.: Inline Integration: A New Mixed Symbolic/Numeric Approach for Solving DAE Systems. Proc. ESM’95; European Simu-lation Multiconf.; 1995.

[16] Johnson J.; Chagnon T.; Vachranukunkiet P.; Nagvajara P.; Nwankpa C.; Sparse LU Decomposition using FPGA; International Workshop on State-of-the-Art in Scientific and Parallel Computing (PARA); 2008

[17] Daga V.; Govindu G.; Prasanna V.; Gangadharpalli S.; Sridhar V.; Floating-point based block LU decomposi-tion on FPGAs; Proc. Intl. Conf. on Engineering Re-configurable Systems; 2004

[18] Gonzalez J.; Núñez R. C. LAPACKrc: Fast linear algebra kernels/solvers for FPGA accelerators. Journal of Physics: Conference Series. 2009

[19] Fischer T.; Entwurf eines FPGA-Cores zur Simulationsbeschleunigung zeitkontinuierlicher Modelle im HiL Kontext. GI Fachtagung Echtzeit 2011 -Herausforderungen durch Echtzeitbetrieb; 2011

[20] Paulin P. G.; Knight J. P. Forcedirected scheduling in automatic data path synthesis. Proc. 24th ACM/IEEE Design Automation Conf. (DAC); 1987

[21] Xilinx; Inc. Synthesis and Simulation Design Guide. UG626 (v13.4); 2012

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