Conference article

A non-overlapping two-phase clock generator with adjustable duty cycle

Magnus Karlsson
University of Kalmar, Sweden

Mark Vesterbacka
Linköping University, Sweden

Wlodek Kulesza
University of Kalmar, Sweden

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Published in: GigaHertz 2003. Proceedings from the Seventh Symposium

Linköping Electronic Conference Proceedings 8:28, p.

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Published: 2003-11-06

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ISSN: 1650-3686 (print), 1650-3740 (online)

Abstract

In this paper; a new robust non-overlapping twophase clock generator with adjustable duty cycle is proposed. The generator is based on a differential negative edge trigged D flip-flop and has small area and power consumption. The maximal clock rate and delay are also improved reaching a clock frequency of 1.0 GHz in a standard 0.35 µm CMOS process. The new clock generator is inherently glitch and spike free and robust against slow clock transitions; that reduces the design effort significantly.

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References

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[3] M. Karlsson; and M. Vesterbacka; “A RobustNon-Overlapping Two-Phase Clock Generator;” in Proc. of Swedish System on Chip Conference SSoCC’03; Sundbyholms slott; Eskilstuna; Sweden; Mars 8-9; 2003.

[4] M. Karlsson; M. Vesterbacka; “Implementation of Bit-Serial Adders using Robust Differential Logic;” in Proc. IEEE Conf. NORCHIP’97. pp. 366-373; Tallin; Estonia; Nov.; 1997.

[5] J. Yuan; and C. Svensson; “New Single-Clock CMOS Latches and Flipflops with Improved Speed and Power Savings;” IEEE J. of Solid-State Circuits; Vol. SC-32; No. 1. pp. 62-69; Jan.; 1997.

[6] M. Afghahi; “A Robust Single Phase Clocking forLow Power; High Speed VLSI Applications;” IEEE J. of Solid-State Circuits; Vol. SC-31; No. 2; pp. 247-254; Feb.; 1996.

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