Leonidas Tsiopoulos
Department of Information Technologies, Åbo Akademi University, Turku, Finland
Ladda ner artikel
Ingår i: NODES 09: NOrdic workshop and doctoral symposium on DEpendability and Security; Linköping; Sweden; April 27; 2009
Linköping Electronic Conference Proceedings 41:1, s. 1-9
Publicerad: 2009-07-14
ISBN:
ISSN: 1650-3686 (tryckt), 1650-3740 (online)
In this paper we present an approach on how executable formal specifications of Network-on-Chip routing schemes can help on deciding efficient placement of processing resources on 3D-integrated systems. We use a routing scheme specified with the B Action Systems formalism and we execute it with the model checking and animating tool ProB in order to obtain traces of operation executions based on different data flow scenarios.
[1] Abrial J.?R. (1996). The B?Book; Cambridge University Press.
[2] Addo?Quaye; C. (2005). Thermal-aware mapping and placement for 3-D NoCdesigns. In Proc. IEEE Int. Syst.-on- Chip Conf.; pp. 25?28.
[3] Back; R.J.R.; Kurki?Suonio; R. (1983). Decentralization of Process Nets with Centralized Control; Proc. of the 2nd Symposium on Principles on Distributed Computing; pp. 131?142.
[4] Butler; M.; Waldén; M. (1996). Distributed System Development in B; Proc. of the 1st conference on the B Method; Nantes; France; pp. 155?168.
[5] ClearSy; Atelier B; http://www.atelierb.societe.com/
[6] Dally; W. J. and Towles; B. (2001). Route packets; not wires: On?chip interconnection networks. In Proc. of the DAC?01; pp. 681?689.
[7] Gutmann; R. J.; Lu; J. Q.; Kwon; Y.; McDonald; J. F.; Cale; T. S. (2001). Threedimensional (3D) ICs: a technology platform for integrated systems and opportunities for new polymeric adhesives. In Proc. Conf. Polymers Adhesives Microelectron. Photon. Pp. 173?180.
[8] Hemani; A.; Jantch; A.; Kumar; S.; Postula; A.; Öberg; J.; Millberg; M.; and Lindqvist; D. (2000). Network on a Chip: An architecture for billion transistor era. In Proc. of the IEEE NorChip Conference.
[9] Leuschel; M.; Butler M. (2005). ProB: A Model Checker for B; Proc. FME?03; LNCS Volume 2805; Springer; pp. 855?874.
[10] Li; F.; Nicopoulos; C.; Richardson; T.; Xie; Y.; Narayanan; V.; Kandemir; M. (2006). Design and Management of 3D Chip Multiprocessors Using Network-in-Memory. ACM SIGARCH Computer Architecture News. Volume 34 ; Issue 2. pp. 130 ? 141.
[11] Murali; S.; Seiculescu; C.; Benini; L.; De Micheli; G. (2009). Synthesis of Networks on Chips for 3D Systems on Chips. Proceedings of the 2009 Conference on Asia and South Pacific Design Automation. pp. 242-247.
[12] Tsiopoulos; L.; Waldén; M. (2006). Formal Development of NoC Systems in B; Nordic Journal of Computing; Vol. 13 (2006). pp. 127?145.
[13] Waldén; M.; Sere; K. (1998). Reasoning about Action Systems using the B Method; Formal methods in System Design; Vol. 13(1); pp. 5?35.
