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FDTD analysis of multichip vertical interconnects

Janusz Rudnicki
Instytut Radioelektroniki Politechniki Warszawskiej, Poland

J. Piotr Starski
Chalmers University of Technology, Microwave Electronics, Sweden

Ladda ner artikelhttp://www.ep.liu.se/ecp_article/index.en.aspx?issue=008;article=077

Ingår i: GigaHertz 2003. Proceedings from the Seventh Symposium

Linköping Electronic Conference Proceedings 8:77, s.

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Publicerad: 2003-11-06

ISBN:

ISSN: 1650-3686 (tryckt), 1650-3740 (online)

Abstract

In this paper we present FDTD simulations for multichip interconnects between a CPW transmission line; CPW transmission line and a CPW chip (CPW-CPW-CPW) using metallic; spherical bumps. We show that the main influence on the performance of the entire CPW-CPW-CPW structure has the first level of interconnection; where the via holes are used. A reduction in return loss can be achieved by using small bump dimensions in the lower CPW-CPW interconnection.

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Referenser

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[2] J. P. Starski; J. Rudnicki; „Numerical Investigation of Flip Chip Connections using FDTD Simulations”; 3rd European Week; 2-6 October 2000; Paris; France

[3] J. P. Starski; J. Rudnicki; „Numerical Analysis of Conductive Adhesive Based Flip Chip Connections”; 9th Topical Meeting on Electrical Performance of Electrical Packaging EPEP 2000; 23-25 October 2000; Scottsdale; Arizona; USA

[4] J. Rudnicki; J. P. Starski; „Vertical interconnection for flip chip connection”; 14th International Conference on Microwaves; Radar and Wireless Communications; Poland; Gdansk; May 2002

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[6] W. Heinrich; A. Jentzsch; H. Richter; „Flip-chip interconnects for frequencies up to W band”; Electronic Letters; vol. 37; pp. 180-181; Feb. 2001

[7] K. G. Heinen; W. H. Schoen; “Multichip assembly with flipped integrated circuits”; ”; IEEE Trans. Hybrids; Manufact. Technol.; vol. 12; no. 4; Dec. 1989

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