FDTD analysis of multichip vertical interconnects

Janusz Rudnicki
Instytut Radioelektroniki Politechniki Warszawskiej, Poland

J. Piotr Starski
Chalmers University of Technology, Microwave Electronics, Sweden

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Ingår i: GigaHertz 2003. Proceedings from the Seventh Symposium

Linköping Electronic Conference Proceedings 8:77, s.

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Publicerad: 2003-11-06


ISSN: 1650-3686 (tryckt), 1650-3740 (online)


In this paper we present FDTD simulations for multichip interconnects between a CPW transmission line; CPW transmission line and a CPW chip (CPW-CPW-CPW) using metallic; spherical bumps. We show that the main influence on the performance of the entire CPW-CPW-CPW structure has the first level of interconnection; where the via holes are used. A reduction in return loss can be achieved by using small bump dimensions in the lower CPW-CPW interconnection.


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