Translating Modelica to HDL: An Automated Design Flow for FPGA-based Real-Time Hardware-in-the-Loop Simulations

Christian Köllner
FZI Forschungszentrum Informatik, Karlsruhe, Germany

Torsten Blochwitz
ITI GmbH, Dresden, Germany

Thomas Hodrius
SET GmbH, Wangen/Allgäu, Germany

Ladda ner artikelhttp://dx.doi.org/10.3384/ecp12076355

Ingår i: Proceedings of the 9th International MODELICA Conference; September 3-5; 2012; Munich; Germany

Linköping Electronic Conference Proceedings 76:37, s. 355-364

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Publicerad: 2012-11-19

ISBN: 978-91-7519-826-2

ISSN: 1650-3686 (tryckt), 1650-3740 (online)


Advances in the development of electric vehicles challenge existing test methodologies and tools. In particular; hardware-in-the-loop test rigs to verify electric motor controllers require real-time drivetrain emulation with response times in the order of one microsecond. Field-programmable gate arrays can fulfill these requirements due to their high parallelism and the possibility to realize efficient and predictable I/O interfaces. We present an integrated methodology which translates Modelica models to VHDL hardware designs. Our methodology combines well-engineered algorithms from Modelica compilation and high-level synthesis for hardware. We demonstrate its capabilities using the example of a DC motor which was synthesized and implemented on a Xilinx Virtex-5 device.


Modelica; FPGA; High-level synthesis; VHDL; Hardware-in-the-Loop; Real-time


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