Research and Development of a SiC Static Induction Transistor

Kristina Dynefors
Chalmers University of Technology, Sweden

Vincent Desmaris
Chalmers University of Technology, Sweden

Joakim Eriksson
Chalmers University of Technology, Sweden

Per-åke Nilsson
Chalmers University of Technology, Sweden

Niklas Rorsman
Chalmers University of Technology, Sweden

Herbert Zirath
Chalmers University of Technology, Sweden

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Ingår i: GigaHertz 2003. Proceedings from the Seventh Symposium

Linköping Electronic Conference Proceedings 8:74, s.

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Publicerad: 2003-11-06


ISSN: 1650-3686 (tryckt), 1650-3740 (online)


A fabrication process for SiC Static Induction Transistors (SITs) is developed and tested. Simulated and measured results of the device are presented. The complete fabrication process involves only 5 lithography steps; due to the self-aligned process used for mesa; ohmic contacts and gates. This makes the process fast and minimize the risk of process errors. Only optical lithography is used in the process; why dimensions are not optimised. Mesa widths of 2; 3; 4 and 5 µm are processed. Since the process is scalable; better performance can be expected with smaller widths achieved by the use electron beam lithography. Preliminary results indicate FET operation with a maximum current density of 110 mA/mm.


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